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    • 专利摘要:
    Integrated structure comprising a pair of neighboring MOS transistors (TRI, TR2), each transistor (TR1, TR2) having a gate region (RG1, RG2) separated from an underlying substrate (1) by a first gate dielectric ( OX1), an additional region (RG3) comprising a gate material, separated from the two gate regions (RG1, RG2) by a second gate dielectric (OX12), and having a continuous element (RG30) located above a part of the two grid regions and a branch (RG31) integral with an area of the lower face of said element and extending between and away from the two grid regions to the first gate dielectric.
    公开号:FR3018952A1
    申请号:FR1452363
    申请日:2014-03-21
    公开日:2015-09-25
    发明作者:Marc Battista；Francois Tailliet
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] Integrated structure comprising neighboring MOS transistors Embodiments of the invention relate to circuits using neighboring MOS transistors or placed close to each other, for example vis-à-vis or substantially vis-à-vis screw, with grid regions preferentially aligned. Such circuits can be, for example, repetitive circuits with constant predetermined steps, such as those that can be found in memory devices, for example within the row and / or column decoders, and in particular the memory devices associating with the device. within a same memory cell, an elementary cell of the static random access memory (SRAM) type and one or more non-volatile elementary memory cells, for example two or four, in particular elementary memory cells of the type electrically erasable and programmable Read Only Memory (EEPROM), double gate. Indeed, it is also possible to find MOS transistors placed close to each other, for example inverters of the elementary memory cell SRAM type. The distance between two neighboring MOS transistors is often limited by lithography constraints imposing minimum distances between the two gate regions or between the channels of the two transistors. These disadvantages also apply when producing transistors made using dual-level gate technologies such as those that can be found in memory devices associating within a single memory cell, an elementary cell of the SRAM type and one or more elementary memory cells (s) nonvolatile (s), for example of the type EEPROM, double gate. An elementary memory cell of the SRAM type is a volatile memory cell, that is to say, losing its data in the event of a power failure, but offering a very fast access speed as well as infinite cycling. A non-volatile elementary memory cell, for example a memory cell of the EEPROM type, makes it possible to keep the data in the event of a power failure but can not be cycled indefinitely. A memory cell associating an elementary cell of the SRAM type and one or more non-volatile cells (for example two or four) makes it possible to cumulate the performances of the two approaches, namely the infinite speed and endurance of the SRAM memory and the non-volatile memory. - Volatility of the non-volatile memory, for example the flash memory or EEPROM. Under normal operating conditions, the writing and reading of data in such a memory cell takes place in the elementary cell of the SRAM type. By cons, especially during a power failure, there is transfer of the contents of the SRAM elementary cell in the non-volatile elementary memory cell or cells associated therewith. Then, during a power supply in particular, there is reloading of the data contained in the nonvolatile memory cells, in the corresponding elementary memory cell SRAM. Examples of architectures of such memory cells associating SRAM memory and non-volatile memory are described in US 4,132,905, US 4,467,451, US 4,980,859, US 7,164,608, US 8,018,768 and in French patent applications filed under No. 1355439, 1355440 and 1356720. When the transistor or transistors of the non-volatile elementary memory cell are one or more floating gate transistors, thereby comprising two levels of polysilicon, for example, all the transistors of the SRAM cell are advantageously made with these two polysilicon levels. The transistors of the SRAM-type cell are then short-circuited between the two polysilicon layers by either electrical contact or physical contact by removing the gate dielectric between the two polysilicon layers. During conventional etching operations, the ends of the effective gates of the transistors, that is to say those formed by the first polysilicon level, round off, which then requires increasing the size of these gate regions. to prevent these rounds from being too close to the channel region, which could lead to leaks. Moreover, the geometry of the gate regions is all the more ill-defined as the stack of polysilicon to be etched is thick. These defects are sometimes corrected by optical proximity corrections (OPC: Optical Proximity Correction) but generally do not allow to obtain in fine structures whose grid regions have square edges. According to one embodiment and embodiment, it is proposed to make neighboring transistors having a significant reduction in the space between the two transistors while avoiding problems of rounded geometry at certain ends of the etched gate regions. According to another embodiment, it is proposed to use such a compact structure of adjacent transistors in a memory device, in particular of the type associating elementary memory cells of the SRAM type and non-volatile elementary memory cells of the EEPROM type. double grid. According to one aspect, there is provided an integrated structure comprising - a pair of neighboring MOS transistors, for example vis-à-vis or substantially vis-à-vis, each transistor having a controllable gate region separated from a substrate under by a first gate dielectric, for example silicon dioxide, an additional region comprising a gate material, for example polysilicon, separated from the two gate regions by a second gate dielectric, for example a stack of silicon nitride-silicon dioxide-silicon nitride.
    [0002] This additional region has a continuous element located above a portion of the two grid regions and a branch secured to an area of the lower face of said element and extending between and away from the two grid regions up to to the first gate dielectric. In this way, a compact structure is obtained in which the space between the two controllable (i.e., non-floating) gate transistors is reduced compared to a conventional structure of the prior art. Even if it is not essential, it is preferable for the two gate regions of the two transistors to be aligned, for simplification of implementation. The orthogonal projections on the substrate of the two profiles vis-à-vis the two grid regions are advantageously free of rounding, that is to say having square edges.
    [0003] In order to be able to control the gate regions of the two transistors, provision is made, according to one embodiment, for each gate region to protrude from said continuous element of said additional region, which makes it possible, for example, to provide two electrically conductive contact pads. , located on either side of said additional region, and respectively in contact with the two grid regions. Moreover, even if it is not essential, it is advantageous to provide an additional contact pad in contact with said additional region. Indeed, this possibly makes it possible to leave this additional floating region, or to connect it to a potential, which makes it possible in particular to form at lower cost, two capacitors in parallel respectively connected with the gates of the two MOS transistors, one of the electrodes of each capacitor being formed by the corresponding gate region.
    [0004] And, such an embodiment finds an advantageous application in particular in the elementary memory cells of the SRAM type associated with nonvolatile elementary memory cells, as will be seen in more detail hereinafter.
    [0005] According to another aspect, there is provided a memory device comprising a memory plane comprising rows and columns of memory cells of the type comprising an elementary memory cell of the SRAM type and at least one mutually coupled non-volatile elementary memory cell. , and processing means configured to manage the memory plane. According to a general characteristic of this other aspect, the nonvolatile elementary memory cells each comprise at least one floating gate transistor and each elementary memory cell of the SRAM type and / or the processing means comprise at least one integrated structure as defined above. This provides a memory device having a smaller footprint compared to conventional devices of the prior art.
    [0006] The elementary memory cell of the SRAM type generally has two inverters cross-coupled. And, according to one embodiment, this elementary memory cell has at least one integrated structure as defined above, the two MOS transistors respectively form the two PMOS transistors of the two inverters. In the elementary cell of the SRAM type, there is a risk of accidental bit switching, that is to say a reversal of the logical value of the data stored in the SRAM memory at the flip-flop formed by the two inverters. this memory. In other words, if at a given time a logic low level is present at the output of one of the inverters and a high logic level is present at the output of the other inverter, a switchover results in a replacement. from the high logic level to the low logical level and vice versa, which results in an inversion of the stored data.
    [0007] These failover errors, still referred to by those skilled in the art, are the Anglo-Saxon denomination of "soft errors", may be caused by disturbances caused by particles such as alpha particles or cosmic rays, or by memory device attacks by laser radiation.
    [0008] One solution currently used to combat these failover errors is to use error correcting codes and to physically move bits belonging to the same error correction group.
    [0009] According to one embodiment, a totally different and simpler solution is proposed to limit the risk of accidental switching of bits of the SRAM cell, this embodiment providing that said at least one integrated structure is a structure having a contact pad. additional contact with the additional region, additional contact pad for connection to a supply voltage or ground. Indeed, such a structure, compact in terms of size, since the first electrode of the capacitor is formed by the gate region of the transistor, makes it possible to achieve in a simple manner, a filtering capacity within the SRAM cell, of value generally much higher than the capacitances achieved at the first level of metallization of the integrated circuit, better controlled and not inducing coupling with the interconnections situated above the SRAM cell.
    [0010] This filtering capacity thus greatly increases the energy required to accidentally switch the flip-flop formed by the two inverters of the SRAM cell. According to one embodiment, the processing means comprise a row decoder and a column decoder which may advantageously comprise integrated structures as defined above. In this respect, the potential of the gate regions of the two transistors of the structure can vary between 0 volts and a maximum value, for example 16 volts, and the additional contact pad is then advantageously designed to receive a potential equal to a chosen value. to avoid a breakdown of the second gate dielectric, for example equal to half of said maximum value, here 8 volts.
    [0011] In another aspect, there is provided an integrated circuit incorporating a memory device as defined above. According to yet another aspect, there is provided a method of producing an integrated structure comprising a pair of neighboring MOS transistors. This method comprises - a) a formation above a substrate of a first gate dielectric, - b) a formation of a first layer of gate material above the first gate dielectric, - c) a localized etching of the first layer so as to form a rectangular slot in said first layer extending in a first direction between two ends, - d) a formation on the first etched layer and on the sides of said slot of a second gate dielectric e) a formation on the second gate dielectric of a second gate material layer; f) an etching of the second gate material layer, the second dielectric layer, the first gate material layer and the gate material layer. first dielectric, according to a profile having a rectilinear portion overlapping said slot between its two ends and extending in a second direction substantially orthogonal to the first directio n, so as to form for each of the two MOS transistors a controllable gate region separated from the substrate by the first gate dielectric and an additional region of gate material, separated from the two gate regions by the second gate dielectric, and having a continuous element located above a portion of the two grid regions and a branch integral with an area of the lower face of said element and extending between and away from the two grid regions to the first dielectric of wire rack. According to one embodiment, the method comprises, after step f) localized etching of the second etched layer of gate material and the second etched dielectric, so as to overflow each gate region of said continuous element of said region. additional, and formation of electrically conductive contact pads on the two protruding portions of the two grids regions.
    [0012] Other advantages and characteristics of the invention will appear on a detailed examination of embodiments and embodiments, in no way limiting, and the appended drawings in which: FIGS. 1 to 15 schematically illustrate various modes of implementation and embodiment of the invention.
    [0013] In FIG. 1, the reference STR denotes the electrical diagram of an integrated structure of which an embodiment within an integrated circuit is illustrated schematically in FIGS. 2 to 5. In this respect, FIG. 3 is a section according to FIG. the line of FIG. 2, FIG. 4 is a section along the line IV-IV of FIG. 2 and FIG. 5 is a partial section along the line VV of FIG. 3. Referring to FIGS. it can be seen that the integrated structure STR here comprises a pair of MOS transistors TR1, TR2. Each transistor TR1, TR2 comprises a gate region RG1, RG2 separated from an underlying substrate 1 by a first gate dielectric OX1 comprising, for example, silicon dioxide. Within the semiconductor substrate 1, for example silicon, are located the active zones ZA1 and ZA2 of the two transistors TR1 and TR2 which are conventionally limited by insulating regions RIS, for example of the shallow trench type (STI: "Shallow Trench Isolation "). The STR structure further comprises an additional region RG3 comprising a gate material, which can, as for the gate regions RG1, contain polysilicon.
    [0014] This additional region RG3 is separated from the two gate regions by a second gate dielectric OX12 which, as illustrated in FIG. 3, may advantageously comprise a stack formed of a layer 0X120 of silicon nitride Si3N4 sandwiched between two layers OX121 and 0X122 silicon dioxide SiO2. The additional region RG3 has a continuous element RG30 located above a portion of the two grid regions RG1 and a branch RG31 integral with an area of the underside of said element RG30 and extending between and away from the two RG1 gate regions to the first gate dielectric 0X1. The grid regions RG1, RG2 overflow here from the continuous element RG30, which offers an easy possibility to control these gate regions by applying a potential or control voltage. In this respect the STR structure comprises for example, on either side of the additional region RG3, two electrically conductive contact pads CNL1, CNL2 respectively in contact with the two grid regions RG1, RG2. These contact pads, based on the protruding portions of the gate regions, make it possible to polarize the two gate regions RG1 and RG2 and here comprise contacts V1, V2 and metal track portions PST1, PST2, located here at first. level of metallization of the integrated circuit.
    [0015] The structure STR also furthermore comprises, in this embodiment, an additional electrically conductive contact pad CNL3 in contact with the additional region RG3 and again making it possible to possibly polarize this additional region RG3 with a potential which may be the supply voltage or the mass. However, this additional contact pad could be left floating. As a variant, CNL3 contact pad could even possibly not be provided if the additional region RG3 actually had to be left floating.
    [0016] Again, the contact pad CNL3 comprises a contact V3 and a metal track PST3, also located here at the first level of metallization of the integrated circuit. It can thus be seen, particularly in FIGS. 1 and 3, that the additional region RG3, the two gate regions RG1 and RG2 and the second gate dielectric OX12 form two capacitors C1 and C2 connected in parallel to the gates of transistors TR1 and TR2 . The first electrode of a capacitor is the corresponding gate region of the transistor and the second electrode of each capacitor is the additional region RG3. The contact pads CNL1, CNL2 and CNL3 make it possible to apply different polarizations on the electrodes of the two capacitors. In FIG. 4, the zones Z S S 1 and Z SD 1 respectively denote the source and drain zones of the transistor TR 1. Contact pads CNLS1, CNLS2, CNLD1 and CNLD2 make it possible to polarize the source and drain zones of the two transistors TR1 and TR2. In particular, in FIG. 5 (on which the RG31 branch has not been represented for simplification purposes), it can be seen that in this embodiment, the two grid regions RG1 and RG2 are aligned and are separated by a slot FNT. Moreover, the orthogonal projections on the substrate of the two profiles PRF1 and PRF2 of the two grid regions which are opposite each other are free of roundings and have square edges. Reference will now be made more particularly to FIGS. 6 to 9 to describe an embodiment of a method for producing such an integrated structure STR within a semiconductor wafer.
    [0017] After conventionally forming the insulating areas RIS in the substrate 1 of the wafer, the first gate dielectric OX1 is formed on the entire semiconductor wafer, in a conventional manner and known per se. Then, a first CHM1 layer of gate material, for example polysilicon, is formed, always full plate, above the first gate dielectric OX1. A localized etching of the first CHM1 layer is then carried out using a conventional photolithography step using a mask comprising a rectangular slot FNM1 extending in a first direction DR1 between two ends EX1 and EX2, so as to form in FIG. this first layer CHM1 a rectangular slot FNG corresponding to the slot FNM1. Then, as illustrated in FIG. 8, the second dielectric of the grids 0X12 is formed, still full plate, on the first etched layer and on the flanks of slot FNG. Then, a second CHM2 layer of grid material is formed, which is always a full plate, on the second gate dielectric OX12 which, in particular, as shown in FIG. 8, fills the rest of the slot FNG between the gate dielectric OX12.
    [0018] Then, as illustrated in FIG. 9, an etching of the second layer of gate material CHM2, of the second dielectric OX12, of the first layer of gate material CHM1 and of the first dielectric OX1, is performed according to a profile FNM2 having a part rectilinear overlapping said slot FNG between its two ends EX1, EX2, this rectilinear portion, here rectangular, extending in a second direction DR2 substantially orthogonal to the first direction. We then obtain (after localized etching of the ends of the RG3 region and the second gate dielectric 0X12 to allow contacting of the contact pads CNL1 and CNL2) the double-level gate structure shown in FIGS. having used two orthogonal geometries FNG and FNM2 for the engravings of the layers CHM1 and CHM2 made it possible not to create rounding in the profiles vis-à-vis the two grid regions, as illustrated in FIG. Moreover, the first mask, comprising the slot FNM1, is associated with a lithography finer than that associated with the mask comprising the profile FNM2. This results in a significant reduction in the spacing between the two transistors. Thus, it is possible to obtain a reduction greater than 50% of the space between the active regions of the two transistors. Reference will now be made more particularly to FIGS. 10 to 15 to illustrate an example of application of such an integrated structure to a DIS memory device incorporated within an integrated circuit CI.
    [0019] As illustrated diagrammatically in FIG. 10, the memory device DIS may comprise in practice a memory plane PM comprising a matrix of cells CELij organized in rows and columns, conventionally associated with processing means (MTR) configured to manage the PM memory plane and comprising in particular a DCDX column decoder and a DCDY line decoder. The line decoders and the column decoders may include integrated structures STR as described above, which provides a saving of space. Such STR structures may also be incorporated into the memory cells CEL ,, j of the DIS device, as will now be described with reference to FIGS. 11 to 15. In FIG. 11, the reference CEL designates a memory cell of FIG. a memory plane, comprising an elementary memory cell of the SRAM CELSR type and at least one non-volatile elementary memory cell CELNV, these two elementary memory cells being mutually coupled. The elementary memory cell CELSR is of conventional structure and comprises a flip-flop BSC formed of two CMOS inverters connected in a crossed manner, as well as two access transistors Ni and N8. The two inverters INV1, INV2 are connected between a power supply terminal intended to be connected to the supply voltage Vdd, and the ground GND. The two access transistors Ni and N8 are respectively connected between the outputs of the two inverters and two bit lines BL and BL, BL designating the bit line complemented by the line BL. The gates of the access transistors Ni and N8 are connected to a word line WL. The writing and reading of data in the elementary memory cell CELSR are conventional operations and known per se. During a power failure or on an external command, the data contained in the elementary memory cell CELSR is transferred and stored in the non-volatile elementary memory cell CELNV. This is a "non-volatile transfer". Then, during a power up, the CELSR elementary memory cell is reloaded with the contents of the CELNV nonvolatile elementary memory cell. And, depending on the configurations chosen during this reloading operation of the CELSR cell, the data may or may not be inverted relative to that which was initially stored in the CELSR memory cell before the non-volatile transfer to the non-volatile memory cell. volatile CELNV. The elementary memory cell CELSR of the cell of FIG. 11 is configured to reduce the risk of accidental switching of the logic states present at the output nodes of the two inverters, for example in the presence of cosmic rays or during a beam attack. laser. In this respect, the CELSR cell comprises a structure STR of the type of those illustrated in FIGS. 1 to 5 and forming the two PMOS transistors P1 and P2 of the two inverters INV1 and INV2. Moreover, whereas, as indicated above, the first electrodes ELC1 of these two capacitors C1 and C2 are respectively formed by the gates of the transistors P1 and P2, the second electrodes ELC2 of these two capacitors C1 and C2 are here connected to the sources of these two transistors P1 and P2, and therefore at the supply voltage Vdd.
    [0020] It would be possible, alternatively, as illustrated in FIG. 12, to connect the two electrodes ELC2 of the two capacitors C1 and C2 to ground GND. These two capacitors C1 and C2 make it possible to increase the total capacity of the flip-flop BSC, which increases the energy required to accidentally toggle the flip-flop B SC. The thickness of the first gate dielectric OX1 (FIG. 3) is typically between 20 Å and 250 Å while the thickness of the second gate dielectric OX12 is typically between 100 Å and 200 Å. Having an SiO 2 -Si 3 N 4 -SiO 2 sandwich for the OX12 dielectric makes it possible to obtain a well-controlled capacity. It should be noted that the use of a structure STR to realize the PMOS transistors of the inverters allows a saving of space, that the RG3 region is left floating or connected to a potential. It would also be possible to make the two NMOS transistors M3 and M6 of the two inverters by means of another STR structure. However, since these two transistors M3 and M6 are on the offset layout, it has been preferable, for reasons of simplicity of implementation, not to use a STR structure for these transistors. NMOS. The invention applies to any type of nonvolatile memory cell having one or more floating gate transistors, such as for example EEPROM cells.
    [0021] FIG. 13 illustrates an exemplary embodiment of a memory cell CEL comprising the elementary memory cell of the SRAM type CELSR and two nonvolatile elementary cells of the EEPROM type CELNV1 and CELNV2 here comprising two floating gate transistors E1 and E2.
    [0022] Such a cell has been described in French Patent Application No. 1356720. Certain features are now recalled. The non-volatile EEPROM cells of the CEL cell are conventional cells, that is to say cells in which the selection transistor has been removed and has a tunnel injection zone between the floating gate and the drain. The sources of these two transistors El and E2 are connected to a supply terminal BAL which is here connected to ground. The control electrodes of the two floating gate transistors E1 and E2 are themselves connected to a first control line CGL. The drains of the two floating gate transistors E1 and E2 are connected to the inputs and the outputs of the two inverters of the CELSR cell by an interconnection stage comprising two NMOS interconnection transistors referenced N2 and N7. More precisely, the two interconnection transistors N2 and N7 are respectively connected between the drains of the two floating gate transistors E1 and E2 and the two outputs of the two inverters P1, N3 and P2, N6. Furthermore, the control electrodes (gates) of these two interconnection transistors N2 and N7 are connected to a second control line PRL. When writing to the elementary memory cell CELSR, which is a conventional write, the command line PRL is to ground blocking the interconnection stage. Similarly, the first CGL command line is also grounded. As is well known by those skilled in the art, a nonvolatile transfer or write consists of an erasure cycle followed by a differential programming cycle since two nonvolatile elementary memory cells are present. For the erase cycle, the line PRL is maintained at ground blocking the interconnection transistors N2 and N7. An erase voltage is then sent on the first command line CGL. During the differential programming cycle, the second command line PRL switches to the supply voltage passing transistors N2 and N7. Then a programming voltage is sent for the first CGL command line.
    [0023] For reloading of the CELSR cell, the first command line CGL switches to a reading reference voltage, typically 1 volt, while the second command line PRL is at a voltage of 2 volts, for example so as to make the transistors N2 and N7.
    [0024] FIG. 14 illustrates another embodiment of a memory cell CEL again incorporating two nonvolatile memory cells of the EEPROM type CELNV1 and CELNV2 here comprising two floating gate transistors E1 and E2.
    [0025] Such a cell has been described in patent application No. 1355439. Certain characteristics are recalled here. Here again, the non-volatile EEPROM cells of the CEL cell are conventional cells, that is to say cells in which the selection transistor has been removed and has a tunnel injection zone between the floating gate and the drain. The sources of these two transistors El and E2 are connected to a supply terminal BAL which is here connected to ground. The control electrodes of the two floating gate transistors E1 and E2 are themselves connected to a first control line CGL. The drains of the two floating gate transistors E1 and E2 are connected to the inputs and the outputs of the two inverters by an interconnection stage comprising here two first NMOS interconnection transistors referenced N2 and N7 and two second NMOS interconnection transistors referenced N4. and N5. More precisely, the first two interconnect transistors N2 and N7 are respectively connected between the drains of the two floating gate transistors E1 and E2 and the two outputs of the two inverters P1, N3 and P2, N6. Furthermore, the control electrodes (gates) of these two interconnection transistors N2 and N7 are connected to a second control line PRL. The two second interconnection transistors N4 and N5 are respectively connected between the drains of the two floating gate transistors E1 and E2 and the two inputs of two inverters P1, N3 and P2, N6. The control electrodes of these two second interconnection transistors N4 and N5 are connected to a third control line RLL. Although the second two interconnection transistors N4 and N5 are not indispensable, they are particularly advantageous because they make it possible to avoid a data inversion when reloading the content of the two non-volatile cells E1 and E2 to the elementary memory cell SRAM CELSR even with a BAL power terminal connected to ground. The writing in the elementary memory cell CELSR is a classical writing.
    [0026] In this respect, the control lines PRL, RLL are grounded, blocking the interconnection stage. Similarly, the first CGL command line is also grounded. Reading data in the CELSR cell is also a classic reading.
    [0027] For the erase cycle, the lines PRL and PLL are held to ground, blocking the interconnection transistors N2, N4, N5 and N7. An erase voltage is then sent on the first command line CGL. For the differential programming cycle, the second command line PRL goes to the supply voltage Vdd while the third command line RLL remains grounded. As a result, the interconnection transistors N2 and N7 are on while the interconnection transistors N4 and N5 are off.
    [0028] Then a programming voltage is sent on the first command line CGL. The floating gate transistors El and E2 are all locked during this differential programming. For reloading of the CELSR cell, the first command line CGL switches to a read reference voltage, typically 1 volt, while the second command line PRL is grounded and the third command line RLL is one. voltage of 2 volts for example so as to pass through transistors N4 and N5 while N2 and N7 transistors are blocked.
    [0029] The voltage of the word line WL is zero. Figure 15 illustrates yet another embodiment of a CEL memory cell. Such a cell has been described on French Patent Application No. 1355440.
    [0030] We recall here some characteristics. This memory cell CEL comprises a single nonvolatile elementary cell of the EEPROM type CELNV comprising here a floating gate transistor El controllable so as to be blocked during programming in the non-volatile elementary memory cell, of data stored in the elementary memory cell of the SRAM type. Here again, the non-volatile cell EEPROM cell CEL is a conventional cell that is to say in which the selection transistor has been removed and having a tunnel injection zone between floating gate and drain. The source of the transistor El is connected to a supply terminal BAL which is here connected to ground. The control electrode of the floating gate transistor El is connected to a first control line CGL. The drain of the floating gate transistor El is connected here to the output (node ND) of the first inverter P1, N3 of the elementary memory cell CELSR via an interconnection stage comprising here a first interconnection transistor. N2. This single interconnection transistor N2 is here an NMOS transistor. The control electrode (gate) of this first interconnection transistor N2 is connected to a second control line PRL. As a result, the interconnection stage is controlled by a signal external to the memory cell CEL, namely by the control voltage present on the second command line PRL. Writing in the elementary memory cell CELSR is again a classical writing. In this respect, the control line PRL is grounded, blocking the interconnection stage. Similarly, the first CGL command line is also grounded. For the erase cycle, the line PRL is maintained at ground, blocking the interconnect transistor N2. An erase voltage is then sent on the first command line CGL.
    [0031] For the programming cycle, the second control line PRL switches to the supply voltage Vdd. As a result, the interconnection transistor N2 is on. Then a programming voltage is sent on the first command line CGL. Prior to reloading, the SRAM CELSR elementary memory cell is initialized (or reset) so as to initialize it in a known state and prevent it from being in a metastable state.
    [0032] This initialization can be performed for example by writing a "1" in the SRAM cell using the conventional write procedure. For reloading, the first command line CGL switches to a reading reference voltage, typically 1 volt, while the second command line PRL is at a voltage of 2 volts, for example to turn on the interconnection transistor. N2. The voltage of the word line WL is zero.
    权利要求:
    Claims (17)
    [0001]
    REVENDICATIONS1. Integrated structure comprising a pair of neighboring MOS transistors (TR1, TR2), each transistor (TR1, TR2) having a controllable gate region (RG1, RG2) separated from an underlying substrate (1) by a first gate dielectric (0X1), an additional region (RG3), comprising a gate material, separated from the two gate regions (RG1, RG2) by a second gate dielectric (0X12), and having a continuous element (RG30) located above a part of the two grid regions and a branch (RG31) integral with an area of the lower face of said element and extending between and away from the two grid regions to the first gate dielectric.
    [0002]
    The structure of claim 1, wherein the two grid regions (RG1, RG2) are aligned.
    [0003]
    3. Structure according to one of the preceding claims, wherein the orthogonal projections on the substrate of the two profiles (PRF1, PRF2) vis-à-vis the two grid regions are free of rounding.
    [0004]
    4. Structure according to one of the preceding claims, wherein the second gate dielectric (012) comprises a silicon nitride layer (0X120) sandwiched between two layers of silicon dioxide (0X121, 0X122).
    [0005]
    5. Structure according to one of the preceding claims, wherein the materials forming the two gate regions (RG1, RG2) and the additional region (RG3) comprise polysilicon.
    [0006]
    6. Structure according to one of the preceding claims, wherein each grid region (RG1, RG2) overflows said continuous element (RG30) of said additional region (RG3).
    [0007]
    7. Structure according to one of the preceding claims, further comprising on either side of said additional region ofeux pads of electrically conductive contacts (CNL1, CNL2) respectively in contact with the two gate regions.
    [0008]
    8. Structure according to claim 7, further comprising an additional electrically conductive contact pad (CNL3) in contact with said additional region.
    [0009]
    A memory device comprising a memory array comprising rows and columns of memory cells (CELi, j) of the type comprising a SRAM elementary memory cell (CELSR) having two inverters cross-coupled and at least one non-volatile elementary memory cell (CELNV) mutually coupled, and processing means (MTR) configured to manage the memory array, characterized in that the non-volatile elementary memory cells each comprise at least one floating gate transistor (El ), and each SRAM elementary memory cell (CELSR) and / or the processing means (MTR) comprise at least one integrated structure (STR) according to one of claims 1 to 7.
    [0010]
    10. Device according to claim 9, wherein each elementary memory cell SRAM type has at least one integrated structure (STR), the two MOS transistors respectively form the two PMOS transistors (P1, P2) of the two inverters.
    [0011]
    11. Device according to claim 10, wherein said at least one integrated structure is a structure (STR) according to claim 7 wherein the additional contact pad (CNL3) is intended to be connected to a supply voltage (Vdd). or to. the mass (GND).
    [0012]
    12. Device according to claim 9, wherein the processing means (MTR) comprises a line decoder (DCDY) and a column decoder (DCDX) having integrated structures (STR) according to one of claims 1 to 7.
    [0013]
    13. Device according to one of claims 9 to 12, wherein said at least one memory cell comprises a single nonvolatile elementary memory cell (El) connected betweenaborne supply (BAL) and the elementary memory cell of the SRAM type (CELSR), the floating gate transistor (El) of the nonvolatile elementary memory cell being controllable so as to be blocked during programming in the nonvolatile elementary memory cell (El), of a data element stored in the SRAM elementary memory cell (CELSR).
    [0014]
    14. Device according to one of claims 9 to 12, wherein said at least one memory cell comprises two groups (E1, E2) each comprising at least one non-volatile elementary memory cell having a floating gate transistor, all floating gate transistors having their first conduction electrode connected to a power supply terminal (BAL) and their control electrode connected to a first control line (CGL), the second conduction electrodes of the floating gate transistors of the elementary memory cells nonvolatile of the two groups being respectively connected at least to the outputs of the two inverters via a controllable interconnection stage (N2, N4, N5, N7), the floating gate transistors (E1, E2) being controllable from to be all blocked during differential programming in the two groups of nonvolatile elementary memory cells, a data st stored in the elementary memory cell of the SRAM type.
    [0015]
    Integrated circuit comprising a memory device according to one of claims 9 to 14.
    [0016]
    16. A method of producing an integrated structure comprising a pair of neighboring MOS transistors, the method comprising a) a formation over a substrate (1) of a first gate dielectric (OX1), b) a formation of a first layer of gate material (CHM1) above the first gate dielectric, c) a localized etching of the first layer to form a rectangular slot (FNG) in said first layer extending in a first direction ( DR1) between two ends, d) a formation on the first etched layer and on the flanks of said slot of a second gate dielectric (OX12), e) a formation on the second gate dielectric of a second layer of material gate (CHM2), f) an etching of the second layer of gate material, the second dielectric, the first layer of gate material and the first dielectric, according to a profile (FNM2) having a rectilinear portion che vauchant said slot between its two ends and extending in a second direction substantially orthogonal to the first direction, so as to form for each of the two MOS transistors a controllable gate region separated from an underlying substrate area by the first dielectric and a further region of gate material, separated from the two gate regions by the second gate dielectric, and having a continuous element located over a portion of the two gate regions and a branch integral with a gate area. the lower face of said element and extending between and away from the two gate regions to the first gate dielectric.
    [0017]
    The method of claim 16, further comprising after step f), localized etching of the etched second layer of gate material and the etched second dielectric so as to overflow each gate region of said continuous element (RG30). ) of said additional region (RG3), and a formation of electrically conductive contact pads (CNL1, CNL2) on the two protruding portions of the two grid regions.
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    同族专利:
    公开号 | 公开日
    US20150270002A1|2015-09-24|
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    US9780098B2|2017-10-03|
    EP2922063B1|2021-05-05|
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    US20160343717A1|2016-11-24|
    US9431108B2|2016-08-30|
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    法律状态:
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    2020-12-18| ST| Notification of lapse|Effective date: 20201109 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1452363A|FR3018952B1|2014-03-21|2014-03-21|INTEGRATED STRUCTURE COMPRISING MOS NEIGHBOR TRANSISTORS|FR1452363A| FR3018952B1|2014-03-21|2014-03-21|INTEGRATED STRUCTURE COMPRISING MOS NEIGHBOR TRANSISTORS|
    US14/657,963| US9431108B2|2014-03-21|2015-03-13|Integrated structure comprising neighboring transistors|
    EP15159143.5A| EP2922063B1|2014-03-21|2015-03-16|Integrated structure comprising neighbouring transistors|
    CN201810167308.3A| CN108281384A|2014-03-21|2015-03-20|Integrated morphology including adjacent transistors|
    CN201520162289.7U| CN204885162U|2014-03-21|2015-03-20|Integrated morphology and memory equipment|
    CN201510126062.1A| CN104934424B|2014-03-21|2015-03-20|Integrated morphology including adjacent transistors|
    US15/229,709| US9780098B2|2014-03-21|2016-08-05|Integrated structure comprising neighboring transistors|
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